1. Technical Field
The disclosure relates to an etching composition, particularly for a kinetically controlled etching of copper and copper alloy surfaces. The disclosure also relates to a process for etching copper and copper alloys, particularly etching at high rates to provide uniform and smooth, isotropic surfaces. The disclosure also relates to an etched copper or copper alloy surface obtained by the process, and a process for generating copper or copper alloy electrical interconnects or contact pads.
2. Discussion of the Background
In the fabrication of thin film wiring for electronic applications and capture pads for interconnections, it is often required to remove a pre-defined thickness of polycrystalline copper by etching. Uniform copper removal may also be accomplished by CMP (chemical mechanical polishing) or e-CMP (electrochemical-mechanical polishing), often with much higher removal rates. Chemical etching, however, has the advantages of process simplicity and absence of mechanical interaction with the substrate. The latter advantage is becoming more important as the mechanical strength of the underlying dielectric layers is being compromised in the pursuit of lower dielectric constants. Any anisotropic etching of the copper or roughening of the copper surface may significantly degrade the performance or reliability of the electronic device.
Generally, etchants (etching compositions or solutions) are either intrinsically anisotropic, or have low etch rates that cannot easily meet manufacturing throughput requirements. In particular, acidic etchants tend to preferentially etch copper in the immediate proximity of grain boundaries and have specificity to grain orientation. Smooth etchants of copper, as disclosed in U.S. Pat. No. 7,056,648 to Cooper et al., may etch at low rates, a fact that limits their use to applications where only small amounts of copper must be etched. In addition, such etchants form a stable oxidized layer, the removal of which requires the use of a post-etch clean as an extra manufacturing step.
Numerous applications in semiconductor fabrication and packaging would benefit from a process able to provide a smooth, isotropic fast etch of copper and copper alloys. Some examples of applications that would benefit include the following:
(1) Selective capping on recessed copper wiring in advanced CMOS (complementary metal oxide semiconductor) devices—to decrease the effective dielectric constant of the intra-layer insulator and increase the reliability of copper wires with regard to stress migration and electromigration;
(2) Post-CMP clean for copper Dual Damascene builds—to suppress dendrite growth for increased reliability, and to remove copper residues on the dielectric spacers for decreased current leakage and increased shorts yield;
(3) Reduced contact resistance between Dual Damascene build levels—to increase contact area at base of vias with upper-level, high resistance liners; and
(4) Isotropic etching of BLM (ball limiting metallurgy) structures for semiconductor interconnects—to remove copper from open areas between capture pads without undue undercutting of patterned interconnects.
Accordingly, a need exists for providing a copper etchant and process for isotropic etching copper and copper alloys at high rates, which are especially useful for improving semiconductor fabrication and packaging.